The present invention relates to static random access memory (SRAM) devices and more specifically, to differentially recessed contacts to enhance multi-gate field effect transistors (FET) SRAM cell stability.
A typical complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) cell consists of six metal-oxide-semiconductor field effect transistors (MOSFETs) including two P-channel field-effect transistors (PFETs) for a pull-up operation, two N-channel field-effect transistors (NFETs) for a pull-down operation, and two NFETs for input/output access (i.e., pass-gate access/access transistors). FIG. 1 is a diagram illustrating a conventional SRAM cell 10. As shown in FIG. 1, the SRAM cell 10 includes two input/output access transistors (NFETs) 12, two pull-down transistors (NFETs) 14, and two pull-up transistors (PFETs) 16. The SRAM cell 10 further includes a plurality of contacts 18 formed on at least one transistor 12, 14, 16. The transistors 12, 14, and 16 include a gate electrode 13 and at least one semiconductor fin 15 formed vertically along a substrate (not shown). A beta ratio of the SRAM cell 10 is defined as the current of the pull-down NFET 14 divided by the current of the access transistor 12. The beta ratio for the conventional multi-gate FET-based SRAM cell 10 is approximately 2.
Today, the multi-gate FET-based SRAM cell has been demonstrated for scaling down in CMOS technology. Conventionally, a multi-gate FET-based SRAM lacks feasibility to have an arbitrary beta ratio due to the fin quantization effect. The beta ratio of planar FET-based SRAM cell, on the other hand, can be arbitrary by changing the device width.